In recent years, the integration degree of system LSIs has remarkably increased. A demand has arisen for a bus configuration which allows a large number of masters to efficiently transfer data to a large number of slaves at high speed. Under these circumstances, multilayered bus systems for allowing a large number of masters to simultaneously transfer data to a large number of slaves are very popular.
As other problems to be considered in system LSIs, a master must finish the transfer of a requested data amount within the requested time. When the amount of data to be transferred is large with respect to the requested time, it becomes difficult to prevent deadline violation by this master. To the contrary, when the amount of data to be transferred is small with respect to the requested time, the master can readily meet its deadline.
For example, patent reference 1 (Japanese Patent Laid-Open No. 10-289203) describes a bus arbitration apparatus which preferentially assigns a bus to a device delayed from the reference. The bus arbitration apparatus in patent reference 1 (Japanese Patent Laid-Open No. 10-289203) comprises a reference counter operating with a clock based on the transfer rate each device is requested of and a transfer data counter for measuring an actually transferred data amount. At the time of bus arbitration, the arbitration apparatus compares the values of these two counters to perform bus arbitration.    Patent Reference 1: Japanese Patent Laid-Open No. 10-289203